This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-063727, filed Mar. 7, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having an insulated gate bipolar transistor with a dielectric isolation structure and a method of manufacturing the same and, more particularly, to a semiconductor device used as a power IC, e.g., an IPD (Intelligent Power Device).
2. Description of the Related Art
Recently, many power semiconductor devices such as insulated gate bipolar transistors (to be referred to as IGBTs hereinafter) are used in purposes such as power conversion and power control of, e.g., inverters and converters. Hence, these power semiconductor devices are essential in the field of electric power.
A conventional lateral IGBT will be explained below with reference to FIGS. 1 and 2.
FIG. 1 is a cross-sectional view showing the structure of a lateral IGBT in a conventional dielectric isolated substrate. The above dielectric isolation structure isolates elements by a dielectric substance. As this dielectric isolation structure, an SOI (silicon on insulator) structure to be described below will be taken as an example.
As shown in FIG. 1, a silicon oxide film 102 is formed on an nxe2x88x92-type silicon layer 101. An nxe2x88x92-type silicon layer 103 is formed on this silicon oxide film 102. An SOI structure is formed by these nxe2x88x92-type silicon layer 101, silicon oxide film 102, and nxe2x88x92-type silicon layer 103.
On this nxe2x88x92-type silicon layer 103, a gate electrode 105 is formed with a gate insulating film 104 interposed between the nxe2x88x92-type silicon layer 103 and the gate electrode 105. In addition, on this nxe2x88x92-type silicon layer 103, an emitter electrode 106 and a collector electrode 107 are formed apart from the gate electrode 105. A field oxide film 108 is formed on the nxe2x88x92-type silicon layer 103 between the gate electrode 105 and the collector electrode 107. The gate electrode 105 is made of a polysilicon film about 4,000 xc3x85 thick.
A p-type base diffusion layer 109 is formed in the nxe2x88x92-type silicon layer 103 from a portion below the gate electrode 105 to a portion below the emitter electrode 106. A p+-type diffusion layer 110 is formed between this p-type base diffusion layer 109 and the emitter electrode 106. Furthermore, an n+-type diffusion layer 111 is formed on the p-type base diffusion layer 109.
An n-type buffer diffusion layer 112 is formed in the nxe2x88x92-type silicon layer 103 below the collector electrode 107. The main purpose of the n-type buffer diffusion layer 112 is to increase the collector-emitter withstand voltage. A p+-type diffusion layer 113 is formed between this n-type buffer diffusion layer 112 and the collector electrode 107. A lateral IGBT in the conventional dielectric isolation substrate is constructed as above.
In this IGBT having the structure shown in FIG. 1, however, a parasitic npn transistor composed of the n+-type diffusion layer 111, the p-type base diffusion layer 109, and the nxe2x88x92-type silicon layer 103 easily operates and sometimes destroys the IGBT by latch up. That is, when this parasitic npn transistor operates, the base current of a parasitic pnp transistor made up of the p+-type diffusion layer 113, the n-type buffer diffusion layer 112, the nxe2x88x92-type silicon layer 103, and the p-type base diffusion layer 109 increases. This amplifies the collector-emitter current of this parasitic pnp transistor. As a consequence, the collector-emitter current increases and destroys the IGBT. Especially when the impurity concentration in the p-type base diffusion layer 109 is low, the latch-up phenomenon causes more easily. To prevent this, the impurity concentration in the p-type base diffusion layer 109 can be increased. However, this makes it difficult to form an inversion layer in the channel region below the gate electrode 105.
To improve a capability of ruggedness by the latch-up phenomenon, therefore, in an IGBT as shown in FIG. 2, a p-type diffusion layer 114 is formed below a p-type base diffusion layer 109 on the side of an emitter electrode 106. This p-type diffusion layer 114 is formed by ion implantation before the formation of a gate electrode 105.
Unfortunately, in this IGBT shown in FIG. 2, if the p-type diffusion layer 114 diffuses to a prospective channel region below the gate electrode 105, the current-voltage characteristics such as the saturation voltage of a collector-emitter voltage Vce and a threshold voltage Vth are influenced. This increases variations in these current-voltage characteristics.
A semiconductor device according to an aspect of the present invention comprises: a first-conductivity-type semiconductor substrate having a principal surface; a second-conductivity-type first semiconductor region and a second-conductivity-type second semiconductor region formed apart from each other in the principal surface of the semiconductor substrate; a second-conductivity-type third semiconductor region formed on the first semiconductor region, the third semiconductor region having an impurity concentration higher than that of the first semiconductor region; a first-conductivity-type fourth semiconductor region formed on the third semiconductor region; a first main electrode formed on the fourth semiconductor region; a second main electrode formed on the second semiconductor region; and a gate electrode formed, at least on the first semiconductor region and on the principal surface of the semiconductor substrate between the fourth semiconductor region and the second semiconductor region, with a gate insulating film interposed between the gate electrode and the first semiconductor region and the principal surface of the semiconductor substrate.
A manufacturing method of a semiconductor device according to an aspect of the present invention comprises: forming a second-conductivity-type first semiconductor region in the surface of a first-conductivity-type semiconductor substrate; forming a gate insulating film on the first semiconductor region and on the semiconductor substrate; forming a gate electrode on the gate insulating film; forming a second semiconductor region having an impurity concentration higher than that of the first semiconductor region in the first semiconductor region, by ion implantation using self-alignment which uses the gate electrode as a mask material; forming a first-conductivity-type third semiconductor region on the second semiconductor region, by ion implantation using self-alignment which uses the gate electrode as a mask material; and forming a second-conductivity-type fourth semiconductor region apart from the first semiconductor region, on the surface of the semiconductor substrate.